ARCHIVED: Where can I find information about using the Intel MIC coprocessors on Stampede (TACC)?

Each compute node on the Extreme Science and Engineering Discovery Environment (XSEDE) digital service Stampede (TACC) is equipped with at least one Xeon Phi SE10P coprocessor, based on Intel's Many Integrated Core (MIC) architecture.

Each MIC coprocessor has a peak performance approximately three times greater than the aggregate peak performance of the two 2.7 GHz E5-2680 Intel Xeon processors that make up each of Stampede's 6,400 compute nodes. Each MIC coprocessor on Stampede is equipped with 8 GB of GDDR5 DRAM, providing a peak bandwidth of 352 GB/s (significantly higher than the 51.2 GB/s peak bandwidth of the Xeon E5 processors).

The MIC coprocessors run the Intel x86 instruction set (with 64-bit extensions), and use the same Intel compilers, tools, and libraries used on Intel and AMD systems. During execution of your code, routines can be redirected (i.e., offloaded) to the MIC coprocessors via automatic offloading or compiler-assisted offloading.

For information about using automatic and compiler-assisted offloading to take advantage of Stampede's MIC coprocessors, see the following sections of the TACC Stampede User Guide in the XSEDE User Portal:

• Innovative Computing Capability with Intel Xeon Phi Coprocessor
• Compiling for Phi Offloading
• Coprocessor (MIC) Programming

For more about using MIC coprocessors in general, see Programming and Compiling for Intel Many Integrated Core Architecture page in the Intel Developer Zone.